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a
FEATURES Low Offset Voltage: 60 V Max Very Low Offset Voltage Drift: 0.7 V/ C Max Low Input Bias Current: 2 nA Max Low Noise: 8 nV/Hz CMRR, PSRR, and AVO > 120 dB Min Low Supply Current: 400 A/Amp Dual Supply Operation: 2.5 V to 15 V Unity Gain Stable No Phase Reversal Inputs Internally Protected Beyond Supply Voltage APPLICATIONS Wireless Base Station Control Circuits Optical Network Control Circuits Instrumentation Sensors and Controls Thermocouples RTDs Strain Bridges Shunt Current Measurements Precision Filters GENERAL DESCRIPTION
Precision Low Noise, Low Input Bias Current Operational Amplifiers OP1177/OP2177/OP4177
FUNCTIONAL BLOCK DIAGRAM 8-Lead MSOP (RM-Suffix)
NC IN IN V 1 8 NC V+ OUT NC
8-Lead SOIC (R-Suffix)
OP1177
4 5 NC = NO CONNECT
NC 1 IN 2 +IN 3 V 4
8 NC
OP1177
7 V+ 6 OUT 5 NC
NC = NO CONNECT
8-Lead MSOP (RM-Suffix)
OUT A IN A IN A V 1 8 V+ OUT B -IN B +IN B
8-Lead SOIC (R-Suffix)
OP2177
4 5
OUT A
1
8 V+
IN A 2 +IN A 3 V 4
OP2177
7 OUT B 6 IN B 5 +IN B
The OPx177 family consists of very high-precision, single, dual, and quad amplifiers featuring extremely low offset voltage and drift, low input bias current, low noise, and low power consumption. Outputs are stable with capacitive loads of over 1,000 pF with no external compensation. Supply current is less than 500 A per amplifier at 30 V. Internal 500 series resistors protect the inputs, allowing input signal levels several volts beyond either supply without phase reversal. Unlike previous high-voltage amplifiers with very low offset voltages, the OP1177 and OP2177 are available in the tiny MSOP 8-lead surface-mount package, while the OP4177 is available in TSSOP14. Moreover, specified performance in the MSOP/TSSOP package is identical to performance in the SOIC package. OPx177 family offers the widest specified temperature range of any high-precision amplifier in surface-mount packaging. All versions are fully specified for operation from -40C to +125C for the most demanding operating environments. Applications for these amplifiers include precision diode power measurement, voltage and current level setting, and level detection in optical and wireless transmission systems. Additional applications include line powered and portable instrumentation
14-Lead SOIC (R-Suffix)
OUT A 1 IN A 2 +IN A 3 V+ 4 +IN B 5 IN B 6 OUT B 7 14 OUT D 13 IN D
OUT A -IN A +IN A V+ +IN B -IN B OUT B
14-Lead TSSOP (RU-Suffix)
1 14 OUT D -IN D +IN D V- +IN C -IN C OUT C
OP4177
7 8
OP4177 OP4177
12 +IN D 11 V 10 +IN C 9 8 IN C OUT C
and controls--thermocouple, RTD, strain-bridge, and other sensor signal conditioning--and precision filters. The OP1177 (single) and the OP2177 (dual) amplifiers are available in the 8-lead MSOP and 8-lead SOIC packages. The OP4177 (quad) is available in 14-lead narrow SOIC and 14-lead TSSOP packages. MSOP and TSSOP packages are available in tape and reel only.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
OP1177/OP2177/OP4177-SPECIFICATIONS otherwise noted.)
Parameter INPUT CHARACTERISTICS Offset Voltage OP1177 OP2177/4177 OP1177/2177 OP4177 Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift OP1177/OP2177 OP4177 OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current POWER SUPPLY Power Supply Rejection Ratio OP1177 OP2177/OP4177 Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density MULTIPLE AMPLIFIERS CHANNEL SEPARATION Symbol Conditions Min VOS VOS VOS VOS IB IOS CMRR AVO VOS/T VOS/T VOH VOL IOUT
(@ VS =
5.0 V, VCM = 0 V, TA = 25 C, unless
Typ*
Max
Unit
-40C < TA < +125C -40C < TA < +125C -40C < TA < +125C -40C < TA < +125C VCM = -3.5 V to +3.5 V -40C < TA < +125C RL = 2 k , VO = -3.5 V to +3.5 V -40C < TA < +125C -40C < TA < +125C IL = 1 mA, -40C < TA < +125C IL = 1 mA, -40C < TA < +125C VDROPOUT < 1.2 V
-2 -1 -3.5 120 118 1,000
15 15 25 25 +0.5 +0.2 126 125 2,000 0.2 0.3
60 75 100 120 +2 +1 +3.5
V V V V nA nA V dB dB V/mV V/C V/C V V mA
0.7 0.9
+4
+4.1 -4.1 10
-4
PSRR PSRR ISY
VS = 2.5 V to 15 V, -40C < TA < +125C VS = 2.5 V to 15 V, -40C < TA < +125C VO = 0 V -40C < TA < +125C RL = 2 k
120 115 118 114
130 125 121 120 400 500 0.7 1.3 0.4 7.9 0.2 0.01 -120
500 600
dB dB dB dB A A V/s MHz V p-p nV/Hz pA/Hz V/V dB
SR GBP en p-p en in CS
0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz DC f = 100 kHz
8.5
*Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors ' data sheets as "typical," give unrealistically low estimates for parameters that can have both positive and negative values. Specifications subject to change without notice.
-2-
REV. B
OP1177/OP2177/OP4177 ELECTRICAL CHARACTERISTICS
Parameter INPUT CHARACTERISTICS Offset Voltage OP1177 OP2177/OP4177 OP1177/OP2177 OP4177 Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift OP1177/OP2177 OP4177 OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Short Circuit Current POWER SUPPLY Power Supply Rejection Ratio OP1177 OP2177/OP4177 Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density MULTIPLE AMPLIFIERS CHANNEL SEPARATION Symbol
(@ VS =
15 V, VCM = 0 V, TA = 25 C, unless otherwise noted.)
Conditions Min Typ* Max Unit
VOS VOS VOS VOS IB IOS CMRR AVO VOS/T VOS/T VOH VOL IOUT ISC
-40C < TA < +125C -40C < TA < +125C -40C < TA < +125C -40C < TA < +125C VCM = -13.5 V to +13.5 V -40C < TA < +125C RL = 2 k , VO = -13.5 V to +13.5 V -40C < TA < +125C -40C < TA < +125C IL = 1 mA, -40C < TA < +125C IL = 1 mA, -40C < TA < +125C VDROPOUT < 1.2 V
-2 -1 -13.5 120 1,000
15 15 25 25 +0.5 +0.2
60 75 100 120 +2 +1 +13.5
V V V V nA nA V dB V/mV
125 3,000 0.2 0.3 0.7 0.9
V/C V/C V V mA mA
+14
+14.1 -14.1 10 35
-14
PSRR PSRR ISY
VS = 2.5 V to 15 V, -40C < TA < +125C VS = 2.5 V to 15 V, -40C < TA < +125C VO = 0 V -40C < TA < +125C RL = 2 k
120 115 118 114
130 125 121 120 400 500 0.7 1.3 0.4 7.9 0.2 0.01 -120
500 600
dB dB dB dB A A V/s MHz V p-p nV/Hz pA/Hz V/V dB
SR GBP en p-p en in CS
0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz DC f = 100 kHz
8.5
*Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors ' data sheets as "typical," give unrealistically low estimates for parameters that can have both positive and negative values. Specifications subject to change without notice.
REV. B
-3-
OP1177/OP2177/OP4177
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+ Differential Input Voltage . . . . . . . . . . . . . . Supply Voltage Storage Temperature Range R, RM, and RU Packages . . . . . . . . . . . -65C to +150C Operating Temperature Range OP1177/OP2177/OP4177 . . . . . . . . . . . -40C to +125C Junction Temperature Range R, RM, and RU Packages . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 10 sec) . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Package Type 8-Lead MSOP (RM) 8-Lead SOIC (R) 14-Lead SOIC (R) 14-Lead TSSOP (RU)
2
1 JA
JC
Unit C/W C/W C/W C/W
190 158 120 240
44 43 36 43
NOTES 1 JA is specified for worst-case conditions, i.e., JA is specified for device soldered in circuit board for surface-mount packages. 2 MSOP is only available in tape and reel.
ORDERING GUIDE
Model OP1177ARM OP1177AR OP2177ARM OP2177AR OP4177AR OP4177ARU
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 8-Lead MINI_SOIC 8-Lead SOIC 8-Lead MINI_SOIC 8-Lead SOIC 14-Lead SOIC 14-Lead TSSOP
Package Option RM-8 SO-8 RM-8 SO-8 R-14 RU-14
Branding Information AZA B2A
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP1177/OP2177/OP4177 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
Typical Performance Characteristics- OP1177/OP2177/OP4177
50 45
NUMBER OF AMPLIFIERS
VSY =
15V
90 VSY = 80 15V
140 VSY = 120
NUMBER OF AMPLIFIERS
15V
NUMBER OF AMPLIFIERS
40 35 30 25 20 15 10 5 0 40 10 20 30 20 10 0 INPUT OFFSET VOLTAGE - 30 V 40
70 60 50 40 30 20 10 0 0.05 0.15 0.25 0.35 0.45 TCVOS - V/ C 0.55
100 80 60 40 20 0
0
0.1 0.2 0.3 0.4 0.5 0.6 INPUT BIAS CURRENT - nA
0.7
TPC 1. Input Offset Voltage Distribution
TPC 2. Input Offset Voltage Drift Distribution
TPC 3. Input Bias Current Distribution
1.8 1.6
OUTPUT VOLTAGE - V
3
VSY = 15V TA = 25 C
60
0 VSY = 15V CL = 0 RL = 45 PHASE SHIFT - Degrees
VSY =
INPUT BIAS CURRENT - nA
15V
50
2
OPEN-LOOP GAIN - dB 40 30 GAIN 20 10 0 10 20
1.4 1.2 1.0 0.8 0.6
1
0
90 PHASE 135
SOURCE
1
SINK 0.4 0.2 0 0.001 0.01 0.1 1 LOAD CURRENT - mA 10
2
3
50
0
50 100 TEMPERATURE - C
150
100k
1M FREQUENCY - Hz
180 10M
TPC 4. Output Voltage to Supply Rail vs. Load Current
TPC 5. Input Bias Current vs. Temperature
TPC 6. Open-Loop Gain and Phase Shift vs. Frequency
120 100
500
VSY = 15V VIN = 4mV p-p CL = 0 RL = AV = 100 AV = 10
450 400
OUTPUT IMPEDANCE -
VSY = 15V VIN = 50mV p-p
CLOSED-LOOP GAIN - dB
80 60 40 20 0 20 40 60 80 1k 10k
AV = 10 AV = 1 AV = 100
300 250 200 150 100 50 0
AV = 1
VOLTAGE - 1V/DIV
350
VSY = 15V CL = 300pF RL = 2k VIN = 4V AV = 1
GND
100k 1M 10M FREQUENCY - Hz
100M
100
1k
100k 10k FREQUENCY - Hz
1M
TIME - 100 s/DIV
TPC 7. Closed-Loop Gain vs. Frequency
TPC 8. Output Impedance vs. Frequency
TPC 9. Large Signal Transient Response
REV. B
-5-
OP1177/OP2177/OP4177
50
SMALL SIGNAL OVERSHOOT - %
VOLTAGE - 100mV/DIV
VSY = 15V CL = 1,000pF RL = 2k VIN = 100mV AV = 1
45 40 35 30 25
VSY = 15V RL = 2k VIN = 100mV p-p
0V 15V
VSY = 15V RL = 10k AV = 100 VIN = 200mV
OUTPUT
+OS 20 15 10 OS 5 0 1 10 100 1k CAPACITANCE - pF 10k
GND
+200mV
0V INPUT TIME - 10 s/DIV
TIME - 100 s/DIV
TPC 10. Small Signal Transient Response
TPC 11. Small Signal Overshoot vs. Load Capacitance
TPC 12. Positive Overvoltage Recovery
140
15V 0V OUTPUT
140
VSY = 120 100
CMRR - dB
15V
120 PSRR 100
VSY =
15V
PSRR - dB
VSY = 15V RL = 10k AV = 100 VIN = 200mV 0V
+PSRR 80 60 40 20 0 10
80 60 40
200mV INPUT TIME - 4 s/DIV
20 0 10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
100
1k 10k 100k FREQUENCY - Hz
1M
10M
TPC 13. Negative Overvoltage Recovery
TPC 14. CMRR vs. Frequency
TPC 15. PSRR vs. Frequency
18
35 VSY = 15V
SHORT CIRCUIT CURRENT - mA
VOLTAGE NOISE DENSITY - nV/ Hz
VSY =
15V
16 14 12 10 8 6 4 2
VSY = 30 ISC 25 ISC 20 15 10 5 0
15V
VNOISE - 0.2 V/DIV
TIME - 1s/DIV
0
50
100 150 FREQUENCY - Hz
200
250
50
0
50 100 TEMPERATURE - C
150
TPC 16. 0.1 Hz to 10 Hz Input Voltage Noise
TPC 17. Voltage Noise Density
TPC 18. Short Circuit Current vs. Temperature
-6-
REV. B
OP1177/OP2177/OP4177
14.40 VSY =
OUTPUT VOLTAGE SWING - V
0.5
15V
OFFSET VOLTAGE - V
0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5
V
14.35 14.30 VOH 14.25 14.20 14.15 14.10 14.05 14.00 50 0 50 100 TEMPERATURE - C 150 VOL
0.4
VSY =
15V
18 VSY = 16
INPUT OFFSET VOLTAGE -
15V
14 12 10 8 6 4 2
100 120 140 20 40 60 80 0 TIME FROM POWER SUPPLY TURN-ON - Sec
0 50 0 50 100 TEMPERATURE - C 150
TPC 19. Output Voltage Swing vs. Temperature
TPC 20. Warm-Up Drift
TPC 21. |VOS | vs. Temperature
133 132 131 130 VSY = 15V
133 132 131 130
PSRR - dB
50
VSY = 15V
45
VSY 5V VSY == 15V
NUMBER OF AMPLIFIERS
40 35 30 25 20 15 10 5 0
CMRR - dB
129 128 127 126 125 124 123 50 0 50 100 TEMPERATURE - C 150
129 128 127 126 125 124 123 50 0 50 100 TEMPERATURE - C 150
40
10 20 30 20 10 0 INPUT OFFSET VOLTAGE -
30 V
40
TPC 22. CMRR vs. Temperature
TPC 23. PSRR vs. Temperature
TPC 24. Input Offset Voltage Distribution
1.4 1.2
OUTPUT VOLTAGE - V
60
1.0 0.8 0.6 0.4 0.2 0 0.001 SINK SOURCE
40 30 GAIN 20 PHASE 10 0 10
45 90 135 180 225 270
CLOSED-LOOP GAIN - dB
VSY = 5V TA = 25 C
OPEN-LOOP GAIN - dB
50
VSY = 5V CL = 0 RL =
120
0
100
PHASE SHIFT - Degrees
80 60 40 20 0 20 40 60 80 1k 10k AV = 10 AV = 100
VSY = 5V VIN = 4mV p-p CL = 0 RL =
AV = 1
0.1 1 0.01 LOAD CURRENT - mA
10
20 100k
1M FREQUENCY - Hz
10M
1M 10M 100k FREQUENCY - Hz
100M
TPC 25. Output Voltage to Supply Rail vs. Load Current
TPC 26. Open-Loop Gain and Phase Shift vs. Frequency
TPC 27. Closed-Loop Gain vs. Frequency
REV. B
-7-
OP1177/OP2177/OP4177
500 450 400 VSY = 5V VIN = 50mV p-p
OUTPUT IMPEDANCE -
AV = 10
AV = 1
300 250 200 150 100 50 0 100 1k 100k 10k FREQUENCY - Hz 1M AV = 100
VOLTAGE - 1V/DIV
350
VOLTAGE - 50mV/DIV
VSY = 5V CL = 300pF RL = 2k VIN = 1V AV = 1
VSY = 5V CL = 1,000pF RL = 2k VIN = 100mV AV = 1
GND
GND
TIME - 100 s/DIV
TIME - 10 s/DIV
TPC 28. Output Impedance vs. Frequency
TPC 29. Large Signal Transient Response
TPC 30. Small Signal Transient Response
50
SMALL SIGNAL OVERSHOOT - %
45 40 35 30
VSY = 5V RL = 2k VIN = 100mV
0V 5V
+OS
VSY = 5V RL = 10k AV = 100 VIN = 200mV OUTPUT
OUTPUT 5V 0V
VSY = 5V RL = 10k AV = 100 VIN = 200mV
25 20 15 10 5 0 1 10 100 1k CAPACITANCE - pF 10k OS
+200mV
0V
0V INPUT TIME - 4 s/DIV
200mV INPUT TIME - 4 s/DIV
TPC 31. Small Signal Overshoot vs. Load Capacitance
TPC 32. Positive Overvoltage Recovery
TPC 33. Negative Overvoltage Recovery
140
200
INPUT
VS = 5V AV = 1 RL = 10k
VSY = 120 100
CMRR - dB
5V
180 160 140
VSY =
5V
VOLTAGE - 2V/DIV
PSRR - dB
80 60 40 20
120 PSRR 100 80 60 40 +PSRR
GND
OUTPUT TIME - 200 s/DIV
0 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M
20 0 10 100 10k 100k 1k FREQUENCY - Hz 1M 10M
TPC 34. No Phase Reversal
TPC 35. CMRR vs. Frequency
TPC 36. PSRR vs. Frequency
-8-
REV. B
OP1177/OP2177/OP4177
18
VOLTAGE NOISE DENSITY - nV/ Hz
VSY =
5V
35
VSY = 16 14 12 10 8 6 4 2
5V
SHORT CIRCUIT CURRENT - mA
30 ISC 25 ISC 20 15 10 5 0 50 0
VSY =
5V
VNOISE - 0.2 V/DIV
TIME - 1s/DIV
0
50
100 150 FREQUENCY - Hz
200
250
50 100 TEMPERATURE - C
150
TPC 37. 0.1 Hz to 10 Hz Input Voltage Noise
TPC 38. Voltage Noise Density
TPC 39. Short Circuit Current vs. Temperature
4.40 VSY = 5V
V
25 VSY =
INPUT OFFSET VOLTAGE -
600 5V 500 VSY = 400 VSY = 300 5V 15V
OUTPUT VOLTAGE SWING - V
4.35 4.30 VOH 4.25 4.20 4.15 4.10 4.05 4.00 50 0 50 100 TEMPERATURE - C 150 VOL
15
10
SUPPLY CURRENT -
A
200 100 0 50 0 50 100 TEMPERATURE - C 150 50 0
20
5
0
50 100 TEMPERATURE - C
150
TPC 40. Output Voltage Swing vs. Temperature
TPC 41. |VOS | vs. Temperature
TPC 42. Supply Current vs. Temperature
450 TA = 25 C 400
A
0 20
350 300 250 200 150 100 50 0 0 5 10 15 20 25 SUPPLY VOLTAGE - V 30 35
CHANNEL SEPARATION - dB
40 60 80 100 120 140 160 10 100 1k 10k 100k FREQUENCY - Hz 1M
SUPPLY CURRENT -
TPC 43. Supply Current vs. Supply Voltage
TPC 44. Channel Separation vs. Frequency
REV. B
-9-
OP1177/OP2177/OP4177
FUNCTIONAL DESCRIPTION
Where BW is the bandwidth in Hertz. NOTE: The above analysis is valid for frequencies larger than 50 Hz. When considering lower frequencies, flicker noise (also known as 1/f noise) must be taken into account. For a reference on noise calculations refer to Bandpass KRC or Sallen-Key Filter section.
Gain Linearity
OP1177 is the fourth generation of ADI's industry standard OP07 amplifier family. OP1177 is a very high-precision, low-noise operational amplifier with the highly desirable combination of extremely low offset voltage and very low input bias currents. Unlike JFET amplifiers, the low bias and offset currents are relatively insensitive to ambient temperatures, even up to 125C. For the first time, Analog Devices' proprietary process technology and linear design expertise have produced a high-voltage amplifier with superior performance to the OP07, OP77, and OP177 in a tiny MSOP 8-lead package. Despite its small size the OP1177 offers numerous improvements including low wideband noise, very wide input and output voltage range, lower input bias current, and complete freedom from phase inversion. OP1177 has the widest specified operating temperature range of any similar device in a plastic surface-mount package. This is increasingly important as PC board and overall system sizes continue to shrink, causing internal system temperatures to rise. Power consumption is reduced by a factor of four from the OP177 while bandwidth and slew rate increase by a factor of two. The low power dissipation and very stable performance versus temperature also act to reduce warm-up drift errors to insignificant levels. Open-loop gain linearity under heavy loads is superior to competitive parts like OPA277, improving dc accuracy and reducing distortion in circuits with high closed-loop gains. Inputs are internally protected from overvoltage conditions referenced to either supply rail. Like any high-performance amplifier, maximum performance is achieved by following appropriate circuit and PC board guidelines. The following sections provide practical advice on getting the most out of the OP1177 under a variety of application conditions.
Total Noise Including Source Resistors
Gain linearity reduces errors in closed-loop configurations. The straighter the gain curve, the lower the maximum error over the input signal range will be. This is especially true for circuits with high closed-loop gains. The OP1177 has excellent gain linearity even with heavy loads, shown in Figure 1. Compare its performance to the OPA277, shown in Figure 2. Both devices were measured under identical conditions with RL = 2 k. The OP2177 (dual) has virtually no distortion at lower voltages. It was compared to the OPA277 at several supply voltages and various loads. Its performance exceeded that of its counterpart by far.
VSY = 15V RL = 2k
V
The low input current noise and input bias current of the OP1177 make it useful for circuits with substantial input source resistance. Input offset voltage increases by less than 1 V max per 500 of source resistance. The total noise density of the OP1177 is:
NEED LABEL FOR THIS AXIS SCALE - V
SCALE -
OP1177
SCALE - V
Figure 1. Gain Linearity
VSY = 15V RL = 2k
en , TOTAL = en + (in RS ) + 4kTRS
2 2
Where, en is the input voltage noise density in is the input current noise density RS is the source resistance at the noninverting terminal k is Boltzman's constant (1.38 10-23 J/K) T is the ambient temperature in Kelvin (T = 273 + C) For RS < 3.9 k, en dominates and
OPA277
en, TOTAL en
For 3.9 k < RS < 412 k, voltage noise of the amplifier, current noise of the amplifier translated through the source resistor, and thermal noise from the source resistor all contribute to the total noise. For RS > 412 k, the current noise dominates and
en, TOTAL in RS
SCALE - V
Figure 2. Gain Linearity
Input Overvoltage Protection
When their input voltage exceeds the positive or negative supply voltage, most amplifiers require external resistors to protect them from damage. The OP1177 has internal protective circuitry that allows voltages as high as 2.5 V beyond the supplies to be applied at the input of either terminal without any harmful effects.
The total equivalent rms noise over a specific bandwidth is expressed as:
E n = (en , TOTAL ) BW
-10-
REV. B
OP1177/OP2177/OP4177
Use an additional resistor in series with the inputs if the voltage will exceed the supplies by more than 2.5 V. The value of the resistor can be determined from the formula: demanded by the circuit's transfer function lies beyond the maximum output voltage capability of the amplifier. A 10 V input applied to an amplifier in a closed-loop gain of 2 will demand an output voltage of 20 V. This is beyond the output voltage range of the OP1177 when operating at 15 V supplies and will force the output into saturation. Recovery time is important in many applications, particularly where the op amp must amplify small signals in the presence of large transient voltages.
R2 100k V R1 200mV
+
RS + 500
(V IN
- VS )
5 mA
With the OP1177's low input offset current of <1 nA max, placing a 5 k resistor in series with both inputs adds less than 5 V to input offset voltage and has a negligible impact on the overall noise performance of the circuit. 5 k will protect the inputs to more than 27 V beyond either supply. Refer to the THD + N section for additional information on noise versus source resistance.
Output Phase Reversal
2 3
4 1 7 V+ VOUT 10k
1k
Phase reversal is defined as a change of polarity in the amplifier transfer function. Many operational amplifiers exhibit phase reversal when the voltage applied to the input is greater than the maximum common-mode voltage. In some instances this can cause permanent damage to the amplifier. In feedback loops, it can result in system lockups or equipment damage. The OP1177 is immune to phase reversal problems even at input voltages beyond the supplies.
VSY = 10V AV = 1
OP1177
Figure 4. Test Circuit for Overload Recovery Time
TPC 12 shows the positive overload recovery time of the OP1177. The output recovers in less than 4 s after being overdriven by more than 100%. The negative overload recovery of the OP1177 is 1.4 s as seen in TPC 13.
THD + Noise
VOLTAGE - 5V/DIV
VIN VOUT
The OP1177 has very low total harmonic distortion. This indicates excellent gain linearity and makes the OP1177 a great choice for high closed-loop gain precision circuits. Figure 5 shows that the OP1177 has approximately 0.00025% distortion in unity gain, the worst-case configuration for distortion.
0.1 VSY = 15V RL = 10k BW = 22kHz
TIME - 400 s/DIV
0.01
Figure 3. No Phase Reversal
Settling Time
Settling time is defined as the time it takes an amplifier output to reach and remain within a percentage of its final value after application of an input pulse. It is especially important in measurement and control circuits where amplifiers buffer A/D inputs or DAC outputs. To minimize settling time in amplifier circuits, use proper bypassing of power supplies and an appropriate choice of circuit components. Resistors should be metal film types as these have less stray capacitance and inductance than their wire-wound counterparts. Capacitors should be polystyrene or polycarbonate types to minimize dielectric absorption. The leads from the power supply should be kept as short as possible to minimize capacitance and inductance. The OP1177 has a settling time of about 45 s to 0.01% (1 mV) with a 10 V step applied to the input in a noninverting unity gain.
Overload Recovery Time
THD + N - %
0.001 0.0001
20
100 FREQUENCY - Hz
1k
6k
Figure 5. THD + N vs. Frequency
Capacitive Load Drive
OP1177 is inherently stable at all gains and capable of driving large capacitive loads without oscillation. With no external compensation, the OP1177 will safely drive capacitive loads up to 1000 pF in any configuration. As with virtually any amplifier, driving larger capacitive loads in unity gain requires additional circuitry to assure stability. In this case, a "snubber network" is used to prevent oscillation and reduce the amount of overshoot. A significant advantage of this method is that it does not reduce the output swing because the resistor RS is not inside the feedback loop. -11-
Overload recovery is defined as the time it takes the output voltage of an amplifier to recover from a saturated condition to its linear response region. A common example is where the output voltage REV. B
OP1177/OP2177/OP4177
Figure 6 is a scope photograph of the output of the OP1177 in response to a 400 mV pulse. The load capacitance is 2 nF. The circuit is configured in positive unity gain, the worst-case condition for stability. Placing an R-C network, as shown in Figure 8, parallel to the load capacitance CL will allow the amplifier to drive higher values of CL without causing oscillation or excessive overshoot. There is no ringing and overshoot is reduced from 27% to 5% using the snubber network. Optimum values for RS and CS are tabulated in Table I for several capacitive loads up to 200 nF. Values for other capacitive loads can be determined experimentally.
Table I. Optimum Values for Capacitive Loads
400mV
+
V 2 3 7 V+ 4 1 VOUT RS CS CL
OP1177
Figure 8. Snubber Network Configuration
CAUTION: The snubber technique cannot recover the loss of bandwidth induced by large capacitive loads.
Stray Input Capacitance Compensation
CL (nF) 10 50 200
0 0 0
VOLTAGE - 200mV/DIV
RS ( ) 20 30 200
CS 0.33 F 6.8 nF 0.47 F
The effective input capacitance in an op amp circuit, Ct, consists of three components. These are: the internal differential capacitance between the input terminals, the internal common mode capacitance of each input to ground, and the external capacitance including parasitic capacitance. In the circuit of Figure 9, the closed-loop gain increases as the signal frequency increases. The transfer function of the circuit is:
VSY = 5V RL = 10k CL = 2nF
1+ indicating a zero at:
R2 (1 + sC t R 1) R1
0 0 0 GND 0 0 0 0 0 0 0 0 0 0 TIME - 10 s/DIV 0 0 0 0
s=
R 2 + R1 1 = R 2R 1C t 2( R 1// R 2) C t
Depending on the value of R1 and R2, the cutoff frequency of the closed-loop gain may be well below the crossover frequency. In this case, the phase margin, m, can be severely degraded resulting in excessive ringing or even oscillation. A simple way to overcome this problem is to insert a capacitor in the feedback path as shown in Figure 10. The resulting pole can be positioned to adjust the phase margin. Setting Cf = (R1/R2)Ct , achieves a phase margin of 90.
VSY = 5V RL = 10k RS = 200 CL = 2nF CS = 0.47 F
+ V1 - Ct R1 R2
Figure 6. Capacitive Load Drive without Snubber
0 0 0
VOLTAGE - 200mV/DIV
V 2 3 7 4 1 VOUT
0 0 0 GND 0 0
OP1177
V+
Figure 9. Stray Input Capacitance
Cf
0 0 0 0 0 0 0 0 TIME - 10 s/DIV 0 0 0 0
R1 R2
Figure 7. Capacitive Load Drive with Snubber
+ V1 -
V 2 Ct 3 7 V+ 4 1 VOUT
OP1177
Figure 10. Compensation Using Feedback Capacitor
-12-
REV. B
OP1177/OP2177/OP4177
Reducing Electromagnetic Interference
A number of methods can be utilized to reduce the effects of EMI on amplifier circuits. In one method, stray signals on either input are coupled to the opposite input of the amplifier. The result is that the signal is rejected according to the amplifier's CMRR. This is usually achieved by inserting a capacitor between the inputs of the amplifier as shown in Figure 11. However, this method may also cause instability depending on the value of capacitance.
R1 R2
+ V1 - C 2 3
V 4 1 VOUT 7 V+
A variation in temperature across the PC board can cause a mismatch in the Seebeck voltages at solder joints and other points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple effects, resistors should be oriented so heat sources warm both ends equally. Input signal paths should contain matching numbers and types of components where possible in order to match the number and type of thermocouple junctions. For example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. Matching components should be located in close proximity and should be oriented in the same manner. Leads should be of equal length so that thermal conduction is in equilibrium. Heat sources on the PC board should be kept as far away from amplifier input circuitry as practical. The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain a constant temperature across the circuit board.
Difference Amplifiers
OP1177
Figure 11. EMI Reduction
Placing a resistor in series with the capacitor (Figure 12) increases the dc loop gain and reduces the output error. Positioning the breakpoint (introduced by R-C) below the secondary pole of the op amp improves the phase margin and hence stability. R can be chosen independently of C for a specific phase margin according to the formula R2 R 2 R= - 1 + ajf 2 R1 where a is the open-loop gain of the amplifier and f2 is the frequency at which the phase of a = m - 180.
R2
Difference amplifiers are used in high-accuracy circuits to improve the common-mode rejection ratio (CMRR).
R2 100k V R1 V1 2 3 7 V+ V2 R3 = R1 R4 R2 = R3 R1 R4 = R1 4 1 VOUT
OP1177
R1 + - R C 2 3
V 4 1 VOUT
Figure 13. Difference Amplifier
V1
7 V+
OP1177
In the single amplifier instrumentation amplifier (circuit of Figure 13), where: R4 R2 = R 3 R1 VO = R2 (V2 -V1) R1
Figure 12. Compensation Using Input RC Network
Proper Board Layout
The OP1177 is a high-precision device. In order to ensure optimum performance at the PC board level, care must be taken in the design of the board layout. To avoid leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a barrier to moisture accumulation and helps reduce parasitic resistance on the board. Keeping supply traces short and properly bypassing the power supplies will minimize power supply disturbances due to output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be connected as closely as possible to the device supply pins. Stray capacitances are a concern at the output and the inputs of the amplifier. It is recommended that signal traces be kept at least 5 mm from supply lines to minimize coupling.
a mismatch between the ratio R2/R1 and R4/R3 will cause the common-mode rejection ratio to be reduced. To better understand this effect, consider the following:
A DM ACM where ADM is the differential gain and ACM is the common-mode gain. CMRR = A DM = VO V and ACM = O V DIFF VCM
1 (V + V2 ) 21
By definition:
VDIFF = V1 - V2 and VCM =
REV. B
-13-
OP1177/OP2177/OP4177
In order for this circuit to act as a difference amplifier, its output must be proportional to the differential input signal. From Figure 13, R2 VO = - V1 + R1 R2 1 + R1 V2 R3 1+ R4 Maximum measurement accuracy requires cold junction compensation of the thermocouple as described below. To perform the cold junction compensation, apply a copper wire short across the terminating junctions (inside the isothermal block) simulating a 0C point. Adjust the output voltage to zero using the trimming resistor R5 and then remove the copper wire. The OP1177 is an ideal amplifier for thermocouple circuits since it has a very low offset voltage, excellent PSSR and CMRR, and low noise at low frequencies. It can be used to create a thermocouple circuit with great linearity. Resistors R1 and R2 and diode D1 shown in Figure 14 are mounted in an isothermal block. (1)
VCC C1 2.2 F R9 200k R3 47k D1 D1 R2 4.02k Cu 10 F R6 50 24 3 10 F R7 80.6k +15V 0.1 F 10 F
Arranging terms and combining the equations above yields: CMRR = R 4 R 1 + R 3R 2 + 2R 4 R 2 2R 4 R 1 - 2R 2R 3
The sensitivity of CMRR with respect to the R1 is obtained by taking the derivative of CMRR, in Equation 1, with respect to R1. CMRR R 1R 4 2R 2R 4 + R 2R 3 = + R 1 R 1 2R 1R 4 - 2R 2R 3 2R 1R 4 - 2R 2R 3 CMRR = R 1 1 (2R 2R 3) R 1R 4
ADR293
() TJ (+) VTC
TR
R8 1k R5 100
1
VOUT
2-
7
TR
Cu R1 50 R4 50
OP1177
10 F
Assuming that: R1 R2 R3 R4 R and R(1 - ) < R1, R2, R3, R4 < R(1 + ). The worst-case CMRR error arises when: R1 = R4 = R(1 + ) and R2 = R3 = R(1 - ). Plugging these values into Equation 1 yields: CMRR MIN 1 2
ISOTHERMAL BLOCK
15V
0.1 F
Figure 14. Type K Thermocouple Amplifier Circuit
Low Power Linearized RTD
A common application for a single element varying bridge is an RTD thermometer amplifier as shown in Figure 15. The excitation is delivered to the bridge by a 2.5 V reference applied at the top of the bridge. RTDs may have thermal resistance as high as 0.5C to 0.8C per mW. In order to minimize errors due to resistor drift, the current through each leg of the bridge must be kept low. In this circuit, the amplifier supply current flows through the bridge. However, at the OP1177 maximum supply current of 600 A, the RTD dissipates less than 0.1 mW of power even at the highest resistance. Errors due to power dissipation in the bridge are kept under 0.1C. Calibration of the bridge can be made at the minimum value of temperature to be measured by adjusting RP until the output is zero. To calibrate the output span, set the full-scale and linearity pots to midpoint and apply a 500C temperature to the sensor or substitute the equivalent 500C RTD resistance. Adjust the full-scale pot for a 5 V output. Finally, apply 250C or the equivalent RTD resistance and adjust the linearity pot for 2.5 V output. The circuit achieves better than 0.5C accuracy after adjustment.
where is the tolerance of the resistors. Lower tolerance value resistors result in higher common-mode rejection (up to the CMRR of the op amp). Using 5% tolerance resistors, the highest CMRR that can be guaranteed is 20 dB. On the other hand, using 0.1% tolerance resistors would result in a common-mode rejection ratio of at least 54 dB (assuming that the op amp CMRR 54 dB). With the CMRR of OP1177 at 120 dB minimum, the resistor match will be the limiting factor in most circuits. A trimming resistor can be used to further improve resistor matching and CMRR of the difference amp circuit.
A High-Accuracy Thermocouple Amplifier
A thermocouple consists of two dissimilar metal wires placed in contact. The dissimilar metals produce a voltage VTC = (TJ - TR ) where TJ is the temperature at the measurement of the hot junction, TR is the one at the cold junction, and is the Seebeck coefficient specific to the dissimilar metals used in the thermocouple. VTC is the thermocouple voltage. VTC becomes larger with increasing temperature.
-14-
REV. B
OP1177/OP2177/OP4177
+15V
REALIZATION OF ACTIVE FILTERS Bandpass KRC or Sallen-Key Filter
500
0.1 F
ADR421
4.12k
4.37k 15V
200
The low offset voltage and the high CMRR of the OP1177 make it an excellent choice for precision filters such as the KRC filter shown in Figure 17. This filter type offers the capability to tune the gain and the cutoff frequency independently.
VOUT
4.12k 100
6 5
4 7 8
1/2 OP2177
100
20
+15V
Since the common-mode voltage into the amplifier varies with the input signal in the KRC filter circuit, a high CMRR is required to minimize distortion. Also, the low offset voltage of the OP1177 allows a wider dynamic range when the circuit gain is chosen to be high. The circuit of Figure 17 consists of two stages. The first stage is a simple high-pass filter whose corner frequency fC is: 1 2 C 1C 2R 1R 2 (2) and whose
5k 49.9k 100 RTD 2 3 8 15V 4 1 VOUT
1/2 OP2177
+15V
Q=K
Figure 15. Low Power Linearized RTD Circuit
Single Op Amp Bridge
R1 R2
(3)
where K is the dc gain. Choosing equal capacitor values minimizes the sensitivity and simplifies Equation 2 to: 1 2C R 1R 2 The value of Q determines the peaking of the gain versus frequency (ringing in transient response). Commonly chosen values for Q are generally near unity. Setting Q = 1 2 ,
The low input offset voltage drift of the OP1177 makes it very effective for bridge amplifier circuits used in RTD signal conditioning. It is often more economical to use a single bridge op amp as opposed to an instrumentation amplifier. In the circuit of Figure 16, the output voltage at the op amp is:
R2 VO = V REF R R1 R1 R + 1 + R 2 (1 + )
where = R/R is the fractional deviation of the RTD resistance with respect to the bridge resistance due to the change in temperature at the RTD. For << 1, the expression above becomes:
R 2 R 2 R1 R1 = VO 1 + + V V REF R 1 R 1 R R 2 R 2 REF R 1+ + R R2
yields minimum gain peaking and minimum ringing. Determine values for R1 and R2 by use of Equation 3. , R1/R2 = 2 in the circuit example. Pick R1 = 5 k 2 and R2 = 10 k for simplicity. The second stage is a low-pass filter whose corner frequency can be determined in a similar fashion. For R3 = R4 = R. For Q = 1
With VREF constant, the output voltage is linearly proportional to with a gain factor of:
fC =
1 2R C3 C4
and Q =
1 C3 2 C4
R 2 R1 R1 V REF 1 + + R R 2 R 2
15V RF 0.1 F
Channel Separation
ADR421
V R R 2 R(1+ ) R 3 7 V+ RF 4 1 VOUT
Multiple amplifiers on a single die are often required to reject any signals originating from the inputs or outputs of adjacent channels. OP2177 input and bias circuitry is designed to prevent feedthrough of signals from one amplifier channel to the other. As a result the OP2177 has an impressive channel separation of greater than -120 dB for frequencies up to 100 kHz and greater than -115 dB for signals up to 1 MHz.
OP1177
Figure 16. Single Bridge Amplifier
REV. B
-15-
OP1177/OP2177/OP4177
R2 10k C3 680pF
V V C2 10nF V1 + - C1 10nF 6 5 8 R1 20k V+ 4 7 R3 33k R4 33k 2 3 8 C4 330pF V+ 4 1 VOUT
1/2 OP2177
1/2 OP2177
Figure 17. Two-Stage Band-Pass Filter
10k
SPICE Model
V 4 2 3 8 V+ 100
V 6 5 V1 50mV + - 8 V+ 4 7 1
The spice macro-model for the OP1177 can be downloaded from the Analog Devices web site at www.analog.com. This model will accurately simulate a number of parameters, both dc and ac.
References on Noise Dynamics and Flicker Noise
1/2 OP2177 1/2 OP2177
S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, McGraw-Hill 1998. The Best of Analog Dialogue, from Analog Devices.
Figure 18. Channel Separation Test Circuit
-16-
REV. B
OP1177/OP2177/OP4177
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead MINI_SOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27
0.028 (0.71) 0.016 (0.41)
14-Lead SOIC (R-14)
0.3444 (8.75) 0.3367 (8.55) 0.1574 (4.00) 0.1497 (3.80)
14 1 8 7
0.2440 (6.20) 0.2284 (5.80)
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
45
0.0098 (0.25) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 PLANE 0.0138 (0.35) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
REV. B
-17-
OP1177/OP2177/OP4177
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead TSSOP (RU-14)
0.201 (5.10) 0.193 (4.90)
14
8
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 7
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
8-Lead SOIC (R-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) 1
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
8 0 0.0500 (1.27) 0.0160 (0.41)
-18-
REV. B
OP1177/OP2177/OP4177 Revision History
Location Data Sheet changed from REV. A to REV. B. Page
Added OP4177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ELECTRICAL CHARACTERISTICS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
11/01--Data Sheet changed from REV. 0 to REV. A.
Edit to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. B
-19-
-20-
C02627-0-4/02(B)
REV. B
PRINTED IN U.S.A.

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